In recent years, an image coding method with significantly improved coding efficiency has been jointly recommended by ITU-T and ISO/IEC as ITU-T REC. H. 264 and ISO/IEC 14496-10 (hereinafter referred as “H. 264”). H. 264 carries out discrete cosine transformation (DCT) and inverse discrete cosine transformation (IDCT) as orthogonal transformation and inverse orthogonal transformation on prediction errors in a target pixel block regardless of a prediction scheme applied to the target pixel block.
Extended H. 264 is expected to carry out orthogonal transformation and inverse orthogonal transformation using individual transform bases for the respective nine types of prediction modes specified for intra-picture prediction (intra-prediction), thus improving the coding efficiency.
However, it is difficult, in connection with implementation, to carry out orthogonal transformation and inverse orthogonal transformation using individual transform bases for the respective plural types of prediction modes. For example, hardware implementation requires not only dedicated hardware for DCT and IDCT required for H. 264 but also dedicated hardware for individual orthogonal transformations and inverse orthogonal transformations for the respective plural types of prediction directions. The addition of the dedicated hardware increases the scale of relevant circuits.
Software implementation enables not only DCT matrices but also individual transform matrices for the respective types of prediction directions to be loaded from a memory as appropriate and held in a cache memory as appropriate. In this case, the desired orthogonal transformation and inverse orthogonal transformation can be implemented by a general-purpose multiplier. However, disadvantageously, costs increase as a result of an increase in memory bandwidth or in cache memory size.